SELF-ALIGNED STRUCTURE FOR BULK FinFET

ABSTRACT

A FinFET structure which includes a bulk semiconductor substrate; semiconductor fins extending from the bulk semiconductor substrate, each of the semiconductor fins having a top portion and a bottom portion such that the bottom portion of the semiconductor fins is doped and the top portion of the semiconductor fins is undoped; a portion of the bulk semiconductor substrate directly underneath the plurality of semiconductor fins being doped to form an n+ or p+ well; and an oxide formed between the bottom portions of the fins.

RELATED APPLICATION

This application is a continuation of U.S. patent application Ser. No.13/860,832 (Attorney docket no. YOR920120148US1), entitled “SELF-ALIGNEDSTRUCTURE FOR BULK FinFET”, filed Apr. 11, 2013, the disclosure of whichis incorporated by reference herein.

BACKGROUND

The present invention relates to bulk FinFET devices and, moreparticularly, relates to bulk FinFET devices having uniform highconcentration well doping to block the electrical path between thesource and drain and minimize the junction leakage current.

In contrast to traditional planar metal-oxide-semiconductor field-effecttransistors (MOSFETS), which are fabricated using conventionallithographic fabrication methods, nonplanar FETs (Field-EffectTransistors) incorporate various vertical transistor structures, andtypically include two or more gate structures formed in parallel. Onesuch semiconductor structure is the “FinFET” which takes its name fromthe multiple thin silicon “fins” that are used to form the respectivegate channels.

More particularly, a FinFET device generally includes one or moreparallel silicon fin structures (or simply “fins”). The fins extendbetween a common source electrode and a common drain electrode. Aconductive gate structure “wraps around” three sides of the fins, andmay be separated from the fins by a standard gate insulator layer. Finsmay be suitably doped to produce the desired FET polarity, as is knownin the art, such that a gate channel is formed within the fins adjacentto the gate insulator.

Fin structures (and thus FinFET devices) may be formed on asemiconductor substrate. The semiconductor substrate may be a silicon oninsulator (SOI) wafer. The silicon on insulator (SOI) wafer comprises asilicon-comprising material layer overlying a silicon oxide layer. Finstructures are formed from the silicon-comprising material layer. TheSOI wafer is supported by a support substrate which may also be siliconor another semiconducting material.

Alternatively, the semiconductor substrate may be a bulk silicon waferfrom which the fin structures are formed. The bulk silicon wafercomprises a monolithic block of single crystal silicon. A FinFET deviceformed from a bulk silicon wafer is referred to herein as a “bulk FinFETdevice”.

Electrical isolation between adjacent fins and between the source anddrain electrodes of unrelated FinFET devices is needed. “Unrelated” asused herein means that the devices are not intended to be coupledtogether. Electrical current leakage is a parasitic effect, whichdegrades performance of an integrated circuit.

BRIEF SUMMARY

The various advantages and purposes of the exemplary embodiments asdescribed above and hereafter are achieved by providing a FinFETstructure which includes: a bulk semiconductor substrate; a plurality ofsemiconductor fins extending from the bulk semiconductor substrate, eachof the plurality of semiconductor fins having a top portion and a bottomportion such that the bottom portion of the semiconductor fins is dopedand the top portion of the semiconductor fins is undoped; a portion ofthe bulk semiconductor substrate directly underneath the plurality ofsemiconductor fins being doped to form an n+ or p+ well; and an oxideformed between the bottom portions of the fins.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

The features of the exemplary embodiments believed to be novel and theelements characteristic of the exemplary embodiments are set forth withparticularity in the appended claims. The Figures are for illustrationpurposes only and are not drawn to scale. The exemplary embodiments,both as to organization and method of operation, may best be understoodby reference to the detailed description which follows taken inconjunction with the accompanying drawings in which:

FIGS. 1A to 1H illustrate a process for forming fins on a bulk siliconsubstrate wherein:

FIG. 1A illustrates a starting structure including a bulk siliconsubstrate, an oxide layer, an amorphous silicon layer and a hard masklayer;

FIG. 1B illustrates the patterning of the amorphous silicon layer andthe hard mask layer;

FIG. 1C illustrates the removal of the hard mask layer, leaving onlystripes of amorphous silicon;

FIG. 1D illustrates the deposition of a conformal layer of nitride;

FIG. 1E illustrates the etching of the nitride to form sidewall spacers;

FIG. 1F illustrates the etching of the stripes of amorphous silicon toleave only the sidewall spacers;

FIG. 1G illustrates the etching of the oxide layer and the silicon bulksubstrate using the sidewall spacers as a mask to result in stripes ofoxide on silicon fins; and

FIG. 1H illustrates the etching of the sidewall spacers and the oxidestripes to result in silicon fins formed from the bulk siliconsubstrate.

FIG. 2 is a plan view of a beginning FinFET structure comprising aplurality of silicon fins on a bulk silicon substrate.

FIG. 3 is a side view of the FinFET structure of FIG. 2 in the directionof arrow B illustrating a fin on the bulk silicon substrate.

FIGS. 4 to 10 illustrate a first exemplary process for forming aself-aligned structure for a FinFET wherein FIGS. 4 to 10 arecross-sectional views in the direction of arrows A-A in FIG. 2 wherein:

FIG. 4 illustrates the formation of an oxide layer between a pluralityof silicon fins formed from a bulk silicon substrate;

FIG. 5 illustrates the formation of a dummy spacer on each of thesilicon fins;

FIG. 6 illustrates the removal of the oxide layer;

FIG. 7 illustrates the formation of an epitaxial layer in the spaceformerly occupied by the oxide layer;

FIG. 8 illustrates the drive-in of the dopants from the epitaxial layer;

FIG. 9 illustrates the removal of the epitaxial layer and, after removalof the epitaxial layer, the resulting doped portions of the silicon finsand the bulk silicon substrate; and

FIG. 10 illustrates the removal of the dummy spacer and the depositionof a second oxide layer.

FIGS. 11 to 14 illustrate a second exemplary process for forming aself-aligned structure for a FinFET wherein FIGS. 11 to 14 arecross-sectional views in the direction of arrows A-A in FIG. 2 wherein:

FIG. 11 illustrates a starting structure as illustrated in FIG. 6 andthen adding a plasma doping layer in the space formerly occupied by theoxide layer;

FIG. 12 illustrates the drive-in of the dopants from the plasma dopinglayer;

FIG. 13 illustrates the removal of the plasma doping layer and, afterremoval of the plasma doping layer, the resulting doped portions of thesilicon fins and the bulk silicon substrate; and

FIG. 14 illustrates the removal of the dummy spacer and the depositionof a second oxide layer.

FIGS. 15 to 18 illustrate a third exemplary process for forming aself-aligned structure for a FinFET wherein FIGS. 15 to 18 arecross-sectional views in the direction of arrows A-A in FIG. 2 wherein:

FIG. 15 illustrates a starting structure as illustrated in FIG. 6 andthen thinning bottom portions of the semiconductor fins;

FIG. 16 illustrates the deposition of an epitaxial layer and thedrive-in of the dopants from the epitaxial layer;

FIG. 17 illustrates the removal of the epitaxial layer and, afterremoval of the epitaxial layer, the resulting doped portions of thesilicon fins and the bulk silicon substrate; and

FIG. 18 illustrates the removal of the dummy spacer and the depositionof a second oxide layer.

FIGS. 19 and 20 are views similar to FIGS. 2 and 3, respectively, exceptthat FIGS. 19 and 20 illustrate the addition of a gate structure.

DETAILED DESCRIPTION

Referring now to FIGS. 1A to 1H, there is illustrated a preferredprocess for fabricating a bulk semiconductor substrate having fins forpracticing the exemplary embodiments. The preferred process may bereferred to as the sidewall image transfer process.

In FIG. 1A, the process begins with a bulk semiconductor substrate 102which preferably is silicon but may be any other semiconductor materialknown now or in the future. For the purposes of the present exemplaryembodiments, it is preferred that the bulk semiconductor substrate 102is silicon and will be referred to as such in the discussion thatfollows. On top of bulk silicon substrate 102 is an oxide layer 110,followed by an amorphous silicon layer 112 and hard mask layer 114,usually a nitride. Not shown in FIG. 1A are photoresist and other layerswhich may be used to pattern the hard mask layer 114.

Referring now to FIG. 1B, the hard mask layer 114 has been patterned andetched down through the amorphous silicon layer 112, stopping on theoxide layer 110.

Referring now to FIG. 1C, the hard mask layer 114 has beenconventionally stripped, leaving only stripes of amorphous silicon 112.Shown in FIG. 1C are only the ends of the stripes of amorphous silicon112 which run perpendicular to the page.

Thereafter, a conformal layer of nitride 116 is deposited over thestripes of amorphous silicon 112, as shown in FIG. 1D.

The conformal layer of nitride 116 is conventionally etched to formsidewall spacers 118, as shown in FIG. 1E, followed by conventionallyetching the stripes of amorphous silicon 112 to result in only thespacers 118 left on the surface of oxide layer 110, as shown in FIG. 1F.

Using the spacers 118 as a mask, the bulk silicon substrate 102 isetched to form silicon fins 120 extending from the bulk siliconsubstrate 102 and stripes of oxide 122 on the silicon fins 120 as shownin FIG. 1G.

Referring now to FIG. 1H, the spacers 118 and stripes of oxide 122 areconventionally etched to result in silicon fins 120 on the remainingbulk silicon substrate 102.

Referring now to FIG. 2, there is illustrated a plan view of a startingFinFET structure 200 comprising a plurality of spaced-apart fins 202 onbulk silicon substrate 204. The fins 202 may be formed in a process suchas that illustrated in FIGS. 1A to 1H.

FIG. 3 is a side view of the FinFET structure 200 of FIG. 2 in thedirection of arrow B illustrating a fin 202 on bulk silicon substrate204.

In a subsequent process flow, the fins 202 will receive a gate structure(not shown) wrapping around the fins 202. Prior to forming of the gatestructure, the fins 202 of FinFET structure 200 may be doped as will bedescribed in the following description. Some of the doped fins and gatestructures formed thereon may result in N-type FinFETs (NFETS) whileothers of the doped fins and gate structures may result in P-typeFinFETs (PFETS). The present exemplary embodiments are applicable toboth NFET and PFET devices.

FIGS. 4 to 10 illustrate a first exemplary process for doping of thefins wherein FIGS. 4 to 10 are cross-sectional views in the direction ofarrows A-A in FIG. 2.

Referring now to FIG. 4, there is illustrated a starting FinFETstructure 400 which includes a bulk silicon substrate 402 having aplurality of silicon fins 404. The silicon fins 404 preferably may beformed using the process in FIGS. 1A to 1H. An oxide 406 has beendeposited over and between the silicon fins 404, planarized by aconventional process such as chemical mechanical polishing so that theoxide 406 is level with the tops of the silicon fins 404 and then etchedback by a conventional process such as reactive ion etching (RIE) sothat the oxide 406 has been pulled back to expose the sidewalls 408 ofthe silicon fins 404. The oxide 406 may be about one half of the heightof the silicon fins 404.

Referring now to FIG. 5, dummy nitride spacers 410 have been formed onthe sidewalls 408 and tops 412 of the silicon fins 408. In one exemplaryembodiment, nitride such as silicon nitride has been deposited over thesilicon fins 404 and bulk silicon substrate 402 and then etched back bya conventional process such as RIE to leave a dummy spacer on thesidewalls 408 and tops 412 of the silicon fins 404. In another exemplaryembodiment, the tops 412 of silicon fins 404 may have a hard mask (notshown) and then additional nitride is deposited and etched by RIE toform dummy spacers 410 on the sidewalls 408 of the silicon fins 404.

Thereafter, the oxide 406 is stripped using, for example, a wet etch ofdilute hydrofluoric acid (dHF) to result in the structure shown in FIG.6.

The FinFET structure 400 then undergoes an epitaxial process to groweither phosphorous-doped silicon (P-silicon) or boron-doped silicongermanium (B—SiGe) on the exposed portions of the silicon fins 404 andthe bulk silicon substrate 402. The FinFET structure 400 is contactedwith hydrofluoric acid (HF) to remove native oxide then undergoes a 700to 800° C. prebake to completely purge out the oxygen on the surface.Once that part is completed, SiH₄ (or GeH₄) and B₂H₆ or SiH₄ and PH₃ isflowed into the chamber at a control temperature of 600° C. for about800 seconds for the epitaxial process at the surface of the silicon toform either epitaxial P-silicon, B-silicon, or B—SiGe. The epitaxialmaterial 414 is shown in FIG. 7 where the oxide 406 (shown in FIG. 5)used to be.

Referring to FIG. 8, the FinFET structure 400 undergoes either a rapidthermal anneal (RTA) at about 1025° C. for a very short time, about amillisecond or a furnace anneal at about 700° C. for about 30 minutes todrive in the dopants (represented by arrows 416) to the bulk siliconsubstrate 402 and the portions of the silicon fins 404 exposed to theepitaxial material 414. The dummy spacer 410 protects the uppersidewalls 408 and the tops 412 of the fins 404 from the epitaxialmaterial 414 and the drive in of the dopants from the epitaxial material414.

The epitaxial material 414 may be stripped by, for example, hydrochloricacid. The bottom portions 418 of the fins 404 become doped after thedrive in of the dopants from the epitaxial material 414. The dopedportion of the bulk silicon substrate 402 forms a well indicated byreference number 420. The well may have a thickness of about 30 nm. Fora PFET device, P-silicon may be used as the epitaxial material 414 andan n+ well 420 is formed. The bulk silicon substrate 402 is p−. For anNFET device, B-silicon germanium or B-silicon may be used as theepitaxial material 414 and a p+ well 420 is formed. The bulk siliconsubstrate 402 is p−. For this process step, it doesn't matter whetherB-silicon or B-silicon germanium is epitaxially deposited since it isthe boron dopant that is of interest; the epitaxial layer is removed ina subsequent process step. For both PFET and NFET devices, the dopantconcentration in the bottom portions 418 of the fins 404 and well 420 isabout 1×10²⁰ atoms/cm³ while for the bulk silicon substrate 402 thedopant concentration is about 1×10¹⁶ atoms/cm³. The actual dopant isboron for the NFET device and phosphorous for the PFET device. Normally,boron would be the dopant for a PFET and phosphorous for the NFET butthe reverse (boron for NFET and phosphorous for PFET) is desired for thewell doping. The structure thus far is shown in FIG. 9.

Referring now to FIG. 10, the dummy spacer 410 may be conventionallyetched by a combination of physical ion bombardment and chemicalreaction at the surface by flowing in CF₄ and O₂/H₂for a silicon nitrideetch. Thereafter, another layer of oxide 422 may be deposited by aprocess such as that used to deposit the oxide 406 in FIG. 4.

Further processing may now take place to form a gate structure thatwraps around each of the fins 404 and additional conventionalsemiconductor processing steps to complete the FinFET structure 400.

FIGS. 11 to 14 illustrate a second exemplary process for doping of thefins wherein FIGS. 11 to 14 are cross-sectional views in the directionof arrows A-A in FIG. 2.

Referring now to FIG. 11, there is illustrated a starting FinFETstructure 600 which includes a bulk silicon substrate 602 having aplurality of silicon fins 604. The silicon fins 604 preferably may beformed using the process in FIGS. 1A to 1H. In this second exemplaryembodiment of FinFET structure 600, the process begins with a structuresubstantially identical to that shown in FIG. 6 and having dummy spacers606. The FinFET structure 600 undergoes plasma doping to deposit adoping layer 612 in contact with the exposed bottom portions of thesilicon fins 604 and bulk silicon substrate 602. Plasma doping is atechnique characterized by the implantation of energetic impurity ionsthat are generated by immersing the substrate into a plasma and applyinga negative bias voltage—pulsed bias in general—to the substrate. Thesystem consists of a chamber, a RF power and a high vacuum pumpingsystem, a high voltage pulse supply and gas supply system. The plasmadoping source is a gas mixture of PH₃ or B₂H₆ and He gas. When thesubstrate is exposed to the plasma, the doping will be either impinginginto or deposit onto the surface to achieve very shallow junctionformation either in planar or vertical structure. The plasma doping willdeposit either layers of phosphorous or boron dopants. The dummy spacers606 protect the sides 608 and tops 610 of the silicon fins 604 frombeing in contact with the doping layer 612.

Referring to FIG. 12, the FinFET structure 600 undergoes either a rapidthermal anneal (RTA) or a furnace anneal, as described previously withrespect to FIG. 8, to drive in the dopants (represented by arrows 614)to the bulk silicon substrate 602 and the portions of the silicon fins604 exposed to the doping layer 612. The dummy spacers 606 protect theupper sidewalls 608 and the tops 610 of the fins 604 from the dopinglayer 612 and the drive in of the dopants from the doping layer 612.

The doping layer 612 may be stripped by, for example, ozone plasmaashing. The bottom portions 616 (in contact with the doping material612) of the fins 604 become doped after the drive in of the dopants fromthe doping layer 612. The doped portion of the bulk silicon substrate602 forms a well indicated by reference number 618. The well may have athickness of about 30 nm. The FinFET structure may be doped in the samemanner as the first exemplary embodiment. The structure thus far isshown in FIG. 13.

Referring now to FIG. 14, the dummy spacer 606 may be conventionallyetched as described previously. Thereafter, another layer of oxide 620may be deposited by a process such as that used to deposit the oxide 406in FIG. 4.

Further processing may now take place to form a gate structure thatwraps around each of the fins 604 and additional conventionalsemiconductor processing steps to complete the FinFET structure 600.

FIGS. 15 to 18 illustrate a third exemplary process for doping of thefins wherein FIGS. 15 to 18 are cross-sectional views in the directionof arrows A-A in FIG. 2.

Referring now to FIG. 15, there is illustrated a starting FinFETstructure 800 which includes a bulk silicon substrate 802 having aplurality of silicon fins 804. The silicon fins 804 preferably may beformed using the process in FIGS. 1A to 1H. In this third exemplaryembodiment of FinFET structure 800, the process begins with thestructure substantially identical to that shown in FIG. 6 and havingdummy spacers 806.

Subsequently, the bottom portions 808 of the silicon fins 804 have beenthinned by exposing the FinFET structure 800 to an etchant thatanisotropically etches the exposed silicon. For purposes of illustrationand not limitation, the etchant may be an etchant comprising a 25 weightpercent solution of potassium hydroxide and water. The FinFET structure800 is exposed to the etchant for a sufficient time to reduce eachexposed silicon surface by about 2 to 3 nanometers (nm). The startingthickness of the silicon fins 804 is about 10 nm and after exposure tothe etchant, the thickness of the bottom portion 808 is now about 4 to 6nm. The surface 810 of the bulk silicon substrate 802 is also reduced byabout 2 to 3 nm due to exposure to the silicon etchant.

The FinFET structure 800 then undergoes an epitaxial process to groweither phosphorous-doped silicon (P-silicon), boron-doped silicongermanium (B—SiGe) or boron-doped silicon (B—Si) on the exposed bottomportions 808 of the silicon fins 804 and the bulk silicon substrate 802.The epitaxial process is the same as described previously. The epitaxialmaterial 812 is shown in FIG. 16. The FinFET structure 800 thenundergoes either a rapid thermal anneal (RTA) or a furnace anneal, asdescribed previously, to drive in the dopants (represented by arrows814) to the bulk silicon substrate 802 and the exposed bottom portions808 of the silicon fins 804. The dummy spacer 806 protects the uppersidewalls 816 and the tops 818 of the fins 804 from the epitaxialmaterial 812 and the drive in of the dopants from the epitaxial material812.

The epitaxial material 812 may be stripped by, for example, hydrochloricacid. The bottom portions 808 of the fins 804 become doped after thedrive in of the dopants from the epitaxial material 812. The dopedportion of the bulk silicon substrate 802 forms a well indicated byreference number 820. The well may have a thickness of about 30 nm. TheFinFET structure 800 may be doped in the same manner as the firstexemplary embodiment. The structure thus far is shown in FIG. 17.

The dummy spacer 806 may be conventionally etched as describedpreviously. Thereafter, another layer of oxide 822 may be deposited by aprocess such as that used to deposit the oxide 406 in FIG. 4. Theresulting structure is shown in FIG. 18.

Further processing may now take place to form the gate structure thatwraps around each of the fins 804 and additional conventionalsemiconductor processing steps to complete the FinFET structure 800.

FIGS. 19 and 20 illustrate the formation of a gate structure 206 thatwraps around the plurality of fins 202. The gate structure 206 may wraparound all or a plurality of fins 202, as shown in FIGS. 19 and 20, orthere may be a separate gate structure for each of the fins 202. Thegate structure 206 may also include a hard mask 208, such as a siliconnitride. The gate structure 206 may be formed in conjunction with any ofthe exemplary embodiments. The ends of the fins 202 may comprise asource and a drain and may further include P-silicon or B—SiGe epitaxialmaterial (not shown).

The exemplary embodiments are advantageous in that uniform highconcentration well doping is achieved to block the electrical pathbetween the source and drain and minimize the junction leakage current.The third exemplary embodiment is particularly advantageous in thatparasitic capacitance is reduced because the proportion of the channelexposed to the well is less due to the thinning of the fins.

It will be apparent to those skilled in the art having regard to thisdisclosure that other modifications of the exemplary embodiments beyondthose embodiments specifically described here may be made withoutdeparting from the spirit of the invention. Accordingly, suchmodifications are considered within the scope of the invention aslimited solely by the appended claims.

What is claimed is:
 1. A FinFET structure comprising: a bulksemiconductor substrate; a plurality of semiconductor fins extendingfrom the bulk semiconductor substrate, each of the plurality ofsemiconductor fins having a top portion and a bottom portion such thatthe bottom portion of the semiconductor fins is doped and the topportion of the semiconductor fins is undoped; a portion of the bulksemiconductor substrate directly underneath the plurality ofsemiconductor fins being doped to form an n+ or p+ well; and an oxideformed between the bottom portions of the fins.
 2. The FinFET structureof claim 1 wherein the bottom portion of each of the plurality ofsemiconductor fins is thinned compared to the top portion of theplurality of semiconductor fins.
 3. The FinFET structure of claim 2wherein a parasitic capacitance of the FinFET structure is reduced dueto the thinned bottom portion of each of the plurality of semiconductorfins.
 4. The FinFET structure of claim 1 wherein the semiconductor finsand bulk semiconductor substrate are silicon.
 5. The FinFET structure ofclaim 1 further comprising a gate that wraps around at least one of thesemiconductor fins.
 6. The FinFET structure of claim 1 wherein each ofthe plurality of semiconductor fins has a source and a drain and whereinthe well blocks the electrical path between the source and drain andminimizes junction leakage current.
 7. The FinFET structure of claim 1wherein the oxide is only in contact with the bulk semiconductorsubstrate and the bottom portions of the fins.
 8. The FinFET structureof claim 1 wherein the oxide is only in contact with the doped portionof the bulk semiconductor substrate and the doped portion of the fins.